The present invention relates to plasma etch processes used in the manufacture of semiconductor integrated circuits. More specifically, the present invention relates to a system level in situ integrated process for etching layered dielectric structures serving as inter-level dielectric layers.
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors and other electronic devices that can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes of the integrated circuits. The increasing level of integration has also resulted in an increase in the number of layers that make up the integrated circuit. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being developed which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past the common materials for inter-level dielectric have been based upon silicon-based oxide materials that serve as electrical insulators, such as undoped silicon oxide, fluorine-doped silicon oxide and other related materials. Recently, interest has developed in insulating materials with even lower dielectric constants (e.g., low-k dielectrics with a k value less than 3), some of which are based upon silicon but others are based upon carbon.
Many advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective dielectric layers. Particularly logic circuitry, such as microprocessors, employ several layers of metallization with intervening inter-level dielectric layers. Small via holes need to be etched through each of the dielectric layers. The via holes are then filled with a conductor, composed typically of aluminum or tungsten in the past but more recently composed of copper. A horizontal wiring layer is formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. The conventional process not only fills the via holes but also overfills them to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photoresist layer over the planar metal layer and etches the exposed metal into a network of conductive interconnects.
In contrast, a recently developed damascene process substitutes chemical mechanical polishing for metal etching. A dual damascene structure, as illustrated in sectioned isometric view of FIG. 1, has been proposed for advanced chips which avoids the metal etching and combines the metallization of the via and horizontal interconnect. There are two general types of dual damascene processes, self-aligned and counterbore, both of which produce the structure of FIG. 1.
A substrate 10 includes a conductive feature 11 in its surface. If substrate 10 already includes a wiring level at its surface, the conductive feature 11 is metallic and may be a previously formed dual damascene metallization. The interconnection between two metallic wiring levels is called a via. Conventionally, the metal forming the metallization has been aluminum and its alloys or tungsten, but many advanced integrated circuits are now being designed with copper metallization. Alternatively, conductive feature 11 may be a doped region in silicon substrate 10, for example, a source or drain. In this case, the interconnection between the silicon layer and a first metallization layer is called a contact. Although some aspects of the present invention apply to contacts, the major portion of the disclosure and the details of the invention are directed to vias, particularly copper vias and underlying copper lines 11.
A lower stop layer 12, a lower dielectric layer 14, an upper stop layer 16, and an upper dielectric layer 20 are deposited over substrate 10 and included conductive feature 11. Stop layers 12, 16 have compositions relative to those of dieleric layers 14, 20 such that an etch chemistry is available which effectively etches a vertical bole in the overlying dielectric layer 14, 20 but stops on the stop layer 12, 16. That is, the etch selectively etches the dielectric layer over the stop layer. Alternatively stated, the dielectric etch is selective to the stop material. As mentioned before, more advanced circuits are being designed with the two dielectric layers 14, 20 being composed of a dielectric material having a lower dielectric constant than that of silicon dioxide. However, the specific examples of the invention described here use undoped silicon oxide, related non-stoichiometric materials SiOx, and related doped silica glasses for the dielectric, such as fluorinated silica glass (FSG), e.g., F-TEOS which exhibits much the same chemistry as SiO2. These materials will be hereafter collectively be referred to a oxides. The typical stop material for oxide is silicon nitide (Si3N4) although non-stoichiometric ratios SiNx are included where x may be between 1.0 and 1.5. These materials will hereafter be referred to as nitrides. An advantage of the combination of oxide and nitride is that both materials can be grown in a single reactor by plasma-enhanced chemical vapor deposition (PECVD). For example, silicon oxide can be grown under PECVD using tetraorthosilicate (TEOS) as the main precursor gas. Silicon nitride can be grown in the same reactor using silane as the main precursor in the presence of a nitrogen plasma. These examples are non-limiting and simply show the advantage of the illustrated vertical structure.
The dual damascene etch structure shown in FIG. 1 is formed in the previously described vertical structure. FIG. 2 is a flowchart illustrating one processing sequence that can be performed to etch the dual damascene structure shown in FIG. 1. As shown in FIG. 2, after all the dual damascene layers 12, 14, 16, 20 are grown in a horizontally unpatterned vertical structure (step 74), a photoresist layer (not shown) is deposited over upper oxide layer 20 and patterned with apertures corresponding to the via holes 18 (step 76). Next an extended via hole is etched from the top of upper oxide layer 20 to the top of lower nitride stop layer 12 using a multistep etch process that must etch very deeply, for example, 2.5 xcexcm through a very narrow hole (e.g., hole widths of 0.25 or 0.18 xcexcm). This multistep etch process (step 78) is rather demanding and must take the possibility of etch stop into consideration. (Etch stop arises from the fact that the high selectivity of fluorocarbon-based oxide etches to underlying silicon or silicon nitride as well as verticality of the side walls depend upon a polymer depositing on non-oxide surfaces and on the side walls. However, if the etching chemistry is too rich, favoring too much polymer formation, the polymer bridges the sidewalls and covers the oxide bottom of he developing hole and prevents further etching.) Earlier steps in this multistep etch process must etch through both the upper oxide layer and the upper nitride etch stop layer while the final step of the process requires good selectivity to underlying lower nitride stop layer 12. Two examples of single chamber, in situ processes suitable for etch step 78 are presented in U.S. application Ser. No. 09/201,590, entitled xe2x80x9cIn situ Dielectric Etch Process for IC Structures Using Copper Interconnects,xe2x80x9d having co-inventors Hung et al. and assigned to Applied Materials, the assignee of the present invention.
At the completion of multistep etch 78, a photoresist layer (not shown in FIG. 1) is deposited over the top of the upper oxide layer 20 and patterned to the area of the trench 22. Next, in a trench etch step (step 82), upper oxide layer 20 is etched down to upper nitride stop layer 16, thereby forming trench 22. After trench etch 82, the photoresist layer is stripped (step 84) in a process that also removes any polymer produced during trench etch 82. Stripping the photoresist in step 84 is sometimes referred to as ashing. Finally, tower nitride layer 12, which lies exposed at the bottom of via hole 18, is removed to expose contact or metal layer 11 (step 86.
After completion of this dual damascene etch structure, trench 22 and vias 18 are filled with a metal such as aluminum or copper. Physical vapor deposition (PVD) is the usual process for depositing the metal though it may be combined with chemical vapor deposition (CVD) or replaced by electro or electroless plating. Barrier layers are usually first conformally coated in the hole being filled. A typical barrier for copper includes Ta/TaN. The metal is deposited to a thickness that overfills the trench 22 and also covers a top planar surface 30 of the upper oxide layer 30. Chemical mechanical polishing (CMP) is applied to the top surface of the wafer. CMP removes the relatively soft exposed metal but stops on the relatively hard oxide layer 20. The result is a horizontal metal interconnect within the trench 22 and multiple vertical metal interconnects (vias) in the via holes 18.
As can be appreciated by those of skill in the art, the dual damascene etch process described above requires differing etch chemistries and etch capabilities for the steps used to etch through the silicon oxide layer, strip the photoresist and etch through the silicon nitride stop layer (steps 82, 84, 86). Because of the different demands such processes place on substrate etching equipment and limitations in the equipment itself, many integrated circuit (IC) fabrication facilities employ separate pieces of equipment or systems within the fab to perform each step of the above described etch sequences. Such an arrangement of equipment provides for an ex situ etch process because substrates must be transferred avid the clean room between the various pieces of equipment. Exposure of the wafers to the air environment during the transfer between vacuum chambers may result in corrosion of the metal features of the partially processed integrated circuit. The well known susceptibility of copper to corrosion in air increases the destructive risk. Also, carbon-based residue that forms on the interior of the reactor chamber over time can redeposit on exposed copper surfaces. Since these carbon based residues can be extremely difficult to remove from copper, their presence can adversely impact upon subsequent formation of electrical contacts to the copper.
Furthermore, such an ex situ process may result in the formation of a polymer at the bottom of the contact or via area 18. Thus, many integrated circuit manufactures that employ an ex situ process for steps 82, 84, 86 further perform a wet solvent etch by, e.g., dipping the substrate in an HF solution, just prior to depositing the metallization in hole 18 and trench 22. This wet solvent etch is shown in FIG. 2 as step 88.
Engineers at Applied Materials, the assignee of the present invention, have developed an oxide etch process that can be implemented in a single etch reactor thus eliminating the problems associated with exposing the substrate to the ambient during the etch process. One version of this single chamber etch process is described in U.S. application Ser. No. 09/201,590, U.S. Pat. No. 6,380,096 referred to above. The process described in the Ser. No. 09/201,590 application provides an improvement in both etching results and cost of ownership as compared to previously known ex situ oxide etch processes. The process also can be satisfactorily used to form dual damascene structures without requiring a wet solvent dip 88 prior to filling hole 18 and trench 22 with metal.
The dual damascene dielectric trench etch, and in particular oxide trench etch, is expected to be one of the primary steps in the fabrication of future advanced integrated circuits and industry sources predict that the market for the oxide etch solution is one of the largest, if not the largest, markets for equipment substrate processing manufacturers. Thus, while the single chamber in situ oxide etch solution described in the above patent application provides a distinct improvement over ex situ processes, alternative methods of performing the oxide etch are desirable.
Cost of ownership (COO) of one or more substrate processing tool(s) to perform a particular process can be defined as the cost of the tool(s) to own and operate to process substrates according to the particular process over a fixed period of time. COO is an important criteria for semiconductor manufacturers when determining what equipment to purchase for a fabrication facility. COO takes into consideration the overall purchase price of the processing tool(s) and their depreciation, the amount of space the tool(s) require in a fab clean room, the cost to operate the tool(s) including the cost to replace consumable parts, cost of various gases and raw materials used by the tool(s), the throughput of the tool(s), the amount of downtime during which the tool(s) cannot be used, the yield of wafers processed with the tool(s) and other criteria. Because of the large investment required to set up and maintain a IC fabrication facility in today""s business environment, semiconductor manufacturing companies consider COO an important criteria in deciding equipment purchases. Accordingly, it is desirable for semiconductor equipment manufacturers to provide low COO solutions for the processes demanded by semiconductor manufacturing companies for the fabrication of modem integrated circuits.
The present invention provides a system level in situ method of performing the dielectric etch process, such as the sequence of steps 82, 84, 86 shown in FIG. 2, in a multichamber substrate processing system that has a significantly reduced cost of ownership as compared to either previously known ex situ systems or single chamber in situ systems. The method transfers the substrate to be processed among different application chambers in the multichamber system under vacuum conditions so as to not expose the substrate to an ambient between the various steps of the etch sequence.
The present inventors performed detailed studies related to the cost of ownership of various hardware configurations that can satisfactorily perform the dielectric etch process of steps 82, 84, 86 for modern integrated circuits having minimum feature sizes of 0.25 xcexcm or below.
In one embodiment the method of the present invention is an integrated etch process performed in a multichamber substrate processing system having first and second etching chambers. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a stop layer and a feature in the substrate to be contacted into the first etching chamber to etch the dielectric layer. The substrate is then transferred from the first etching chamber to the second etching chamber under vacuum conditions and, in the second etching chamber, is exposed to reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the stop layer is etched through to the feature to be contacted in the second of said multichamber substrate processing system. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps. In one particular embodiment, the system level in situ process of the invention is designed to perform an oxide etch process where the dielectric layer etched in step 82 is a silicon oxide film such as an undoped silicon oxide layer, a fluorine-doped silicon oxide layer, a carbon-doped silicon oxide layer or a porous silicon oxide layer.
In one embodiment, the first chamber is a high performance etch chamber that has the capability of performing the relatively demanding oxide etch step, such as step 82. In one version of this embodiment, the first chamber is a magnetically enhanced reactive ion etch (MERIE) chamber. In another version of this embodiment the first chamber includes separately controlled plasma source power and plasma bias power and a two stage vacuum pump system that includes both mechanical and turbo pumps. The second chamber, on the other hand, is simpler in design and has only a singe mechanical vacuum pump. In one embodiment the second chamber also includes a remote plasma system as opposed to separate plasma source and bias power controls while in a different embodiment the second chamber is a parallel plate etch chamber having a single frequency plasma source power control without a separate control for bias power. In this manner, cost of ownership can be reduced because an in situ system provides significant benefits as compared to an ex situ system including throughput, process performance and space requirements, among others. Furthermore, such a multichamber system level in situ process provides a reduced cost of ownership as compared to a single chamber system because the single chamber system includes hardware capabilities that while being necessary for a relatively demanding etch step such as the oxide etch are not required for a less demanding dielectric etch step such as the photoresist strip or nitride open steps.